The present invention relates, in general, to a silicon-on-insulator (SOI) type semiconductor device and, more specifically, to a body-and-gate-coupled thick oxide structure providing electrostatic discharge (ESD) protection in a network.
Protection networks are typically used in integrated circuits to protect internal components from ESD. In bulk semiconductor material, components may be fabricated to dissipate excess charge during an ESD event. Common types of components used for ESD protection include metal oxide semiconductor field effect transistors (MOSFETs) and thick field oxide (TFO) punch-through devices. In each of these components, the breakdown voltage of the component is determined by the breakdown voltage of a p-n junction within the component. The area of the p-n junction is usually large enough to be able to dissipate the excess charge during an ESD event.
With increased demand for higher speed operation for a semiconductor device, integrated circuits formed on a SOI substrate are attracting attention. The components used for ESD protection for bulk semiconductor devices cannot readily be used by themselves in SOI devices. Much of the area of the p-n junction is lost, because of the buried oxide layer immediately underneath the diffused regions. Consequently, a much smaller area is available to dissipate the excess charge from the ESD event. Because the energy does not dissipate as effectively, the device may overheat and permanent damage may occur.
Various SOI structures have been fabricated which are capable of providing ESD protection. One such structure is disclosed in U.S. Pat. No. 5,760,444 issued to Okumura on Jun. 2, 1998. Okumura describes a separate ESD diode device that is integrated with a MOSFET during the fabrication process. The diode is in electrical connection with the MOSEET through the drain region. When an excess potential is applied to the drain region of the MOSFET, the diode is forward biased to provide a path for electric charges running in the diode. As a result, the SOI semiconductor device has a resistance to electrostatic breakdown. The disadvantage of this device is that it requires extra process step during fabrication; it also lacks flexibility in how the device may be connected to other devices while still providing ESD protection.
Another structure is disclosed in U.S. Pat. No. 5,773,326 issued to Gilbert et al. on Jun. 30, 1998. Gilbert et al. describes a SOI structure which is partitioned into an ESD protection portion and a circuitry portion. The ESD protection portion requires a thick SOI layer to work. The thick SOI layer serves to distribute the ESD current and heat over a large area, thereby improving the ability of the SOI structure to withstand an ESD event.
Yet another structure is disclosed in U.S. Pat. No. 5,726,844 issued to Smith on Mar. 10, 1998. Smith describes a protection circuit, for an SOI device, which uses a body-tied MOSFET and zener diodes in the protection circuit. Because the MOSFET has a thin-gate oxide, several zener diodes are required to protect for over-voltage and under-voltage conditions.
Still another structure is disclosed in U.S. Pat. No. 5,683,918 issued to Smith et al. on Nov. 4, 1997. Smith et al. describe a body-tied MOSFET used in a protection network of a SOI device. The ESD protection device has a vulnerable thin gate oxide and requires a large silicon layout area to be effective.
Another approach for protecting SOI circuitry from ESD is found in U.S. Pat. No. 5,811,857. The ""857 patent issued to Assaderaghi et al. on Sep. 22, 1998 and is incorporated herein by reference. Assaderaghi et al. disclose a SOI circuit which includes a body-coupled-gated (BCG) diode formed from a SOI MOSFET for providing ESD protection. Both NMOSFETs and PMOSFETs may be used to create a forward-biased operation of the diode. Referring to FIGS. 1a-1d (which correspond to FIGS. 2, 3, 5 and 6 of Assaderaghi et al.), two configurations of the BCG diodes are disclosed. FIG. 1a illustrates the circuit schematic of an NMOSFET 100. As shown, NMOSFET 100 comprises a source 108, drain 106, body 104, and gate 102. The drain, body, and gate are connected at node A. When node A is greater in voltage than node B, NMOSFET 100 turns on, thus providing ESD protection. Effectively, NMOSFET 100 may be represented by the diode symbol, as shown in FIG. 1b. 
Similarly, as shown in FIGS. 1c and 1d, a PMOSFET 110 comprises a source 108, drain 106, body 104, and gate 102. The drain, body, and gate are connected at node A. When node B is greater in voltage than node A, PMOSFET 110 turns on, thus providing ESD protection. Effectively, PMOSFET 110 may be represented by the diode symbol, as shown in FIG. 1d. 
It will be appreciated, however, that the NMOSFET and the PMOSFET disclosed by Assaderaghi et al. are both formed with thin-gate oxides and, therefore, are both vulnerable to high voltage ESD events. Moreover, the MOSFETs require that the body contact the gate and the drain. This requirement limits the flexibility of the MOSFETs.
A need still exists for forming a protection network for a SOI device that will allow the device to be protected from ESD potentials that may reach an input/output pad of an integrated circuit. It would be advantageous to have a semiconductor structure which provides adequate ESD protection, but requires a small area for heat dissipation. It would also be advantageous if the structure could be fabricated in a process which could easily be integrated with existing semiconductor processes.
To meet this and other needs, and in view of its purposes, the present invention is directed to a SOI field effect transistor structure providing ESD protection. The structure has a source, a drain, a body, and a gate. The gate is formed from a thick oxide layer and a metal contact. The gate is formed during the back-end-of-the-line (BEOL) process. The transistor may be a p-type transistor or an n-type transistor. The transistor may have its drain tied to either the gate, the body, or both the gate and body. When used as a protection device, the drain is tied to a signal pad and the source is tied to a potential reference.
The process for forming the thick oxide field effect transistor includes the following steps. First, a SOI structure having a semiconductor island is formed by shallow trench isolation; the semiconductor island is of a first conductivity type. Next, a separate source region and a separate drain region in the island are formed using a dopant having a second conductivity type; the remaining region of the first conductivity type forms the body region. An insulating layer is deposited above the island. The insulating layer is etched to form a thick oxide gate region above the body region. Finally, metal leads are formed to contact the source, drain, body, and gate regions.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, but are not restrictive, of the invention.